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FEDERALLY
SPONSORED RESEARCH OR DEVELOPMENT
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SEQUENCE LISTING
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MICROFICHE/COPYRIGHT REFERENCE
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BACKGROUND OF THE INVENTION
The present invention relates to communications systems, all of which are inherently limited in their capacity (or rate) of information transfer by channel impairments. More specifically, the present invention relates to information transfer
between a plurality of Cable Modems (alternatively referred to as "CM") and a Cable Termination System (alternatively referred to as "CMTS" or "headend").
Communication systems are subjected to impairments, generally of a brief or transitory duration. One example of such impairment is often referred to by the generic term "noise". Noise sometimes emanates for example, from within electrical
components themselves, such as amplifiers and even passive resistors. Another example of such impairment is referred to as "interference", which is usually taken to be some unwanted manmade emission, from another communications system such as radio or
from switching circuits in a home or automobile for example. "Distortion" is a yet another example of such impairment, and includes linear distortion in the channel, such as pass-band ripple or non-flat group delay for example, and nonlinear distortion,
such as compression in an overdriven amplifier for example. It is contemplated that there are many other types of impairments that may also adversely affect communications in a channel.
Often, such impairments may by dynamic in nature. In many cases, the impairment may be at one level of severity most of the time. In this instance, the communications system may be designed or optimized in some fashion to operate at that
specific level of impairment. Occasionally, however, one or more of impairments may become so severe as to preclude the operation of such communications system optimized for the more ordinary level of impairments.
Previously, when a large interference or burst of noise occasionally impinges upon the receiver (a CM for example), it is known to simply blank out the received signal to mitigate such large out-of-the ordinary bursts of received power. Often,
analog processing means are used, almost at, if not right at, the receiver input. This may be done especially to protect CM's or other sensitive receiver front-ends from damage. While this technique may provide some benefit in circumstances where the
noise or interference power dwarfs the signal-of-interest power, it does not protect against the many other impairments that have power more on the order of the signal-of-interest power (or even much less). Thus blanking does not, by itself, provide the
receiver with a means to improve its overall performance in the presence of the lost information, i.e., the information content concurrent with the large noise burst.
One known technique, a forward error correction technique (alternatively referred to as "FEC") has been applied, even unknowingly, to solve this problem. FEC techniques incorporate soft-decision decoding, such as is common with convolutional
error correction codes and the Viterbi decoding algorithm. In such correction techniques, as the error power in the received signal increases, such increase is passed directly into the decision process.
Such encoding and decoding techniques have been in common practice for years, and are widely applied without thought to temporary fidelity changes in the channel. Fortunately, in the event of a change in the channel fidelity, the soft-decision
decoding takes into consideration the larger error power in making signal decisions. However, unfortunately, often with a change in channel conditions, there is duration of multiple symbol intervals (in a digital communications system example) where the
degradation persists. During this time some symbols may be so severely erred that they actually appear close to another possible (but wrong or incorrect) symbol. In such event, the soft-decision decoder actually "thinks" it has received a low error
power, and may rate the wrong signal with a high confidence. This becomes much more likely as the constellation density (of a QAM constellation for example) is increased for high rate communications,
Additional techniques, such as a Time Division Multiple Access technique (alternatively referred to as "TDMA") have been applied to solve this problem. In this technique, one or more carrier frequencies are shared among a plurality of CMs.
Known standards, DOCSIS 1.0 and 1.1 for example, each of which are incorporated herein in their entirety, define the physical layer, and additional layers, in which a plurality of CMs transmit data upstream to and receive data downstream from the CMTS or
headend. In this technique, each upstream carrier frequency or channel assignment is general shared by a plurality of CMs, each being granted time slots wherein they may use the channel. These grants are allocated and made known to the CMs via the
downstream broadcast transmissions. Some of the grants only enable a single CM to transmit, while other time slot grants are in contention mode. That is some, or all, of the CMs may attempt to use the grant. However, if more than one CM attempts to
use a grant in the contention mode, all the CMs will likely be unsuccessful in channel use.
Yet another technique, such as direct-sequence spread-spectrum modulation technique discussed by J. Young and J. Lehnert, in their paper titled "Analysis of DFT-Based Frequency Excision Algorithms for Direct-Sequence Spread-Spectrum
Communications," IEEE Trans. Comm., vol. 46, pp. 1076-1087, August 1998, the complete subject matter of which is incorporated herein by reference in its entirety, has also been applied to solve this problem. In this technique, frequency excision is
used to eliminate narrow-band energy, thus enhancing the capacity of direct-sequence spread-spectrum modulation to reject narrow-band interference. However, this disclosed technique focuses on particular waveforms having energy concentrated about a
narrow band.
Yet still another technique, such as such as Code-Division Multiple Access technique (alternatively referred to as "CDMA") discussed by M. Lops, G. Ricci and A. Tulino, in their paper titled "Narrow-Band-Interference Suppression in Multiuser CDMA
Systems," IEEE Trans. Comm., vol. 46, pp. 1163-1175, September 1998, the complete subject matter of which is incorporated herein by reference in its entirety, has also been applied to solve this problem. In this technique, a decision is made regarding
the bit(s) transmitted by each user over a communication system. This decision is based on the projection of the observables on to the orthogonal complement to the subspace spanned by the other users' signatures and the narrow-band interference. The
disclosed technique recognizes that the blanking and iterative processing may be performed with an orthogonal basis set decomposition of the frequency domain.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present
application with reference to the drawings.
BRIEF SUMMARY OF THE INVENTION
These and other advantages and novel features of the present invention, as well as details of an illustrated embodiment thereof, will be more fully understood from the following description and drawings in which a system for mitigating impairment
in a communication system constructed according to the present invention is described. The system includes a delay block, a signal level block, a moving average window block, an impulse noise detection block, and a combiner. The delay block is operable
to receive and delay each chip of a plurality of chips in a spreading interval. This spreading interval may have a duration of 128 chips, such as in an SCDMA system. However, the system may operate according with other spread spectrum or CDMA systems
as well. Further, the system may operate across different spreading sequences whose boundaries are affected by an impairment.
The signal level block is operable to determine a signal level of each chip of the plurality of chips in the spreading interval. The moving average window block communicatively couples the signal level block and is operable to determine a
composite signal level for a chip window corresponding to the chip. The impulse noise detection block communicatively couples to the signal level block and to the moving average window block. The impulse noise detection block is operable to receive the
signal level of each chip of the plurality of chips and spreading interval, to receive the composite signal level corresponding to each chip of the plurality of chips, and to produce an erasure indication for each chip of the plurality of chips of the
corresponding chip window. One purpose of the impulse noise detection block is to determine which chips of the plurality of chips in the spreading interval are impacted by impulse noise and resultantly are not indicative of the value of a spread symbol. After making this/these determination(s), the impulse noise detection block generates corresponding erasure indication(s). The combiner communicatively couples to the delay block and to the impulse noise detection block and is operable to erase chips of
the plurality of chips of the spreading interval based upon the erasure indication.
The erased and kept chips are then passed to a despreader that despreads the chips across the spreading interval to produce a symbol for the spreading interval. Alternately, the chips may be covered with a corresponding orthogonal code prior to
being received by the system and then linearly combined after the chip erasure/keeping operations of the system have been completed.
In determining the signal level of the chip, the signal level block may magnitude-square a measured level of each chip. In one embodiment, the impulse noise detection block is operable to, for each chip of the plurality of chips: (1) compare the
signal level of the chip to a first threshold to produce a first comparison result; (2) compare the composite signal level corresponding to the chip to a second threshold to produce a second comparison result; and (3) produce the erasure indication based
upon the first comparison result and the second comparison result In various embodiments, the first and second comparison result may be either separately used to indicate an erasure or combined to indicate an erasure.
The moving average window block operates to receive the signal level of each chip, e.g., receiving the magnitude-square of the measured level of each chip. The moving average window block sums the signal level of the plurality of chips in the
chip window to produce a signal level summation result. The moving average window block then averages the signal level summation result across the chip window to produce a composite signal level of the plurality of chips of the corresponding chip
window. With this embodiment, the impulse noise detection block may be operable to compare the composite signal level of the plurality of chips of the corresponding chip window to a third threshold to produce a third comparison result and to determine a
fourth comparison result based upon third comparison results of adjacent chips. Further, with this embodiment, the impulse noise detection block is operable to produce the erasure indication based upon the fourth comparison result An additional
operation includes producing the erasure indication by considering first comparison results and second comparison results of neighboring chips. These particular comparison results consider where the edge of the impulse noise impairment in the spreading
interval occurs.
Still another embodiment includes a method of operation. In addition, other aspects, advantages, and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction
with the accompanying drawings.
BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS
FIG. 1 illustrates a block diagram of a generic communication system that may be employed in connection with one embodiment of the present invention.
FIG. 2 illustrates a block diagram of an impairment mitigation system in accordance with one embodiment of the present invention.
FIG. 3 illustrates a flow diagram of one embodiment of a method that may be performed using the system of FIG. 2, in accordance with one embodiment of the present invention.
FIG. 4 illustrates a flow diagram of another embodiment of a method that may be performed using the system of FIG. 2, in accordance with one embodiment of the present invention.
FIGS. 5A & 5B illustrate flow diagrams for impairment mitigation in accordance with specific embodiments of the present invention.
FIG. 6 illustrates a block diagram of an impairment mitigation system in accordance with another embodiment of the present invention.
FIGS. 7A & 7B illustrate a flow diagram of a method of impairment mitigation for use in connection with digital communications in accordance with one specific embodiment of the present invention.
FIGS. 8A & 8B illustrate a flow diagram of a method of impairment mitigation used in connection with digital communications in accordance with another specific embodiment of the present invention.
FIG. 9 illustrates a flow diagram of a method that uses a fidelity metric to modify branch metrics in the decoding process, in accordance with one embodiment of the present invention.
FIG. 10 illustrates a block diagram of an impairment mitigation system that uses preliminary decoding in generating error power estimates, in accordance with one embodiment of the present invention.
FIG. 11 illustrates a flow diagram illustrating one embodiment a method of impairment mitigation that may be employed using the system of FIG. 10 in accordance with one embodiment of the present invention.
FIG. 12 illustrates a high-level flow diagram illustrating one embodiment of an alternate method of impairment mitigation that may be employed using a system similar to that illustrated in FIG. 10 in accordance with one embodiment of the present
invention.
FIGS. 13A & 13B illustrate a flow diagram illustrate an alternate embodiment of a method of impairment mitigation similar to that illustrated in FIG. 12 that may be employed using a system similar to that illustrated in FIG. 10 in accordance with
one embodiment of the present invention.
FIG. 14 is a block diagram illustrating a system for mitigating impairment in a communication system constructed according to the present invention.
FIG. 15 is a schematic diagram illustrating one particular embodiment of the system for mitigating impairment in a communication system illustrated in FIG. 15.
FIG. 16 is a flow diagram illustrating operation according to a first embodiment of the present invention for mitigating impairment in a communication system.
FIG. 17 is a flow diagram illustrating operation according to a second embodiment of the present invention for mitigating impairment in a communication system.
FIG. 18 is a block diagram illustrating the manner in which a system for mitigating impairment of a communication system may interface with other components of a communication system according to the present invention.
DETAILED
DESCRIPTION OF THE INVENTION
The following description is made with reference to the appended figures.
According to one embodiment of the present invention, impairment, burst noise, or other distortion-inducing mechanism of a duration of one up to several chips (6 chips for example) is detected. Means are provided to correct symbol decisions even
in the presence of such impacted or distorted chips. More specifically, one embodiment of the present invention relates to means for detecting at least one and up to several chip(s) with increased impairment, distortion, or noise as provided below. In
the embodiments provided below, it is contemplated that a chip plays the roll of a symbol, although other embodiments are also contemplated as discussed.
One embodiment of the present invention relates to a spreading technique to transmit symbols at the same time on the same frequency. More specifically, one embodiment of the present invention relates to a Synchronous Code Division Multiple
Access technique for communication (alternatively referred to as "SCDMA"). More specifically, this invention relates to SCDMA communications used, in one embodiment, with a DOCSIS 2.0 physical layer standard (alternatively referred to as the "DOCSIS
standard"), which is incorporated herein by reference in its entirety. The DOCSIS standard defines the physical layers in which pluralities of CMs transmit data upstream to and receive data downstream from the CMTS or headend.
In one embodiment of the present invention using SCDMA, about 128 spreading codes are available for modulating each upstream-transmitted symbol. In this embodiment, up to 128 symbols may be transmitted simultaneously, each symbol using its own
spreading code. Each spreading code consists of a sequence of +1 or -1 valued chips, such that there are 128 such chips in each spreading code. In this embodiment, the symbol amplitude and angle are modulated using a vector, applying the vector or its
additive inverse (i.e., 180 degree rotation) to the symbol.
In one embodiment, the spreading codes are orthogonal if perfectly time-aligned, and thus the 128 symbols will not interfere with each other, even though they are transmitted at the same time on the same channel. For example, two waveforms are
orthogonal to each other if, after multiplying them by each other and integrating, the result of the integration is zero. In the SCDMA used with one embodiment of the present invention, at least one but up to 128 spreading codes may be used at one time. These spreading codes may be allocated to one CM, such that that CM is granted all the spreading codes (128 for example), up to the spreading codes be allocated to 64 different CMs, such that two spreading codes are granted to each CM. QAM symbols of
two bits per symbol and more are spread with the assigned codes, one spreading code per QAM symbol, although other arrangements are contemplated.
In one embodiment using SCDMA, the spreading codes are cyclical shifts of one 127-chip spreading code, except for one additional chip. Thus, in this embodiment, the spreading codes are nearly cyclical shifts of one another.
For SCDMA to work efficiently, all the spreading codes should be synchronized as they arrive at the receiver. Timing misalignments result in inter code interference (alternatively referred to as "ICI"), which may degrade performance.
Various channel impairments also degrade performance, and special receiver techniques may be employed to limit or mitigate the degradation caused by such channel performance.
FIG. 1 illustrates a block diagram of a generic communication system that may be employed in connection with one embodiment of the present invention. The system comprises a first communication node 101, a second communication node 111, and at
least one channel 109 that communicatively couples the nodes 101 and 111. The communication nodes may be, for example, cable modems, DSL modems or any other type of transceiver device that transmits or receives data over one or more channels (generally
referred to as CMs).
The first communication node 101 comprises a transmitter 105, a receiver 103, and a processor 106. The processor 106 may comprise, for example, a microprocessor. The first communication node 101 communicates with or is communicatively coupled
to a user 100 (e.g., a computer) via communication link 110, and to the channel 109 via communication links 107 and 108. Of course, communication links 107 and 108 may be combined into a single communication link.
Similarly, the second communication node 111 comprises a transmitter 115, a receiver 114, and a processor 118. The processor 118, like processor 106, may comprise, for example, a microprocessor. The second communication node 111 likewise is
communicatively coupled to the at least one channel 109 via communication links 112 and 113. Again, like communication links 107 and 108, the communication links 112 and 113 may also be combined into a single communication link. The communication node
111 may also be communicatively coupled to a user 120 (again a computer, for example) via communication link 121. In the case when communication node 111 is a headend, for example, user 120 may not be present.
During operation of the illustrated embodiment of FIG. 1, the user 100 may communicate information to the user 120 (or the headend) using the first communication node 101, the at least one channel 109 and the second communication node 111.
Specifically, the user 100 communicates the information to the first communication node 101 via communication link 110. The information is transformed in the transmitter 105 to match the restrictions imposed by the at least one channel 109. The
transmitter 105 then communicates the information to the at least one channel 109 via communication link 107.
The receiver 114 of the second communication node 111 receives, via communication link 113, the information from the at least one channel 109 and transforms it into a form usable by the user 120. Finally, the information is communicated from the
second communication node 111 to the user 120 via the communication link 121.
Communication of information from user 120 to user 100 may also be achieved in a similar manner. In either case, the information transmitted/received may also be processed using the processors 106/118.
FIG. 2 illustrates a block diagram of an impairment mitigation system 200 in accordance with one embodiment of the present invention. The system 200 may be contained, for example, in one or both of the communication nodes of FIG. 1. Error power
estimates may be generated for analog modulations on a sample-by-sample basis. A receiver 201 receives an input at input 203 of either noise (when no signal is present) or a signal with time varying distortion and/or noise, for example. The receiver
201 uses the input to generate error power estimates, and may do so either on a bit by bit basis or using a sequence of bits (or on a symbol by symbol basis or using a sequence of symbols, in a digital communications example). A sliding window 205
receives the error power estimates. The error power estimates are processed in a fidelity processor 207 and a metric for channel fidelity is continuously generated as the window progresses (i.e., over time). The behavior of the metric versus time may
be catalogued (see catalogue 209) and/or analyzed and used to optimize the transmission waveform. The behavior of the metric versus time may also be used to enhance receiver performance in real-time, near-real time, or even in a post-reception,
post-processing mode.
A delay 208 between the input error power estimates of the window 205 and the corresponding channel fidelity metric is known for a given fidelity processor, and is provided back (made known) to a remainder of the system. The system uses the
evolving fidelity metric in its processing, which may be aided by soft decisions designated 211. Soft decisions comprise, for example, erasure decoding or standard soft decision decoding, such as Viterbi decoding. In any case, the receiver outputs an
estimate of the transmitted signal (reference numeral 213).
While FIG. 2 illustrates a system having some components and functionality located outside of the receiver, it is contemplated that such system may have additional components or functionality located within the receiver, or may in fact be
entirely contained within the receiver. In addition, it is also contemplated that the estimation of the error power and the processing shown as being performed within the receiver of FIG. 2 may instead be performed outside of the receiver.
FIG. 3 illustrates a flow diagram of one embodiment of a method that may be performed using the system of FIG. 2, in accordance with the present invention. In one operation of the method, the error power of an input to the system is estimated as
illustrated by block 301. A fidelity metric is determined, using the error power estimate as illustrated by block 303. The determined fidelity metric is then used to decode the input as illustrated by block 305. The method illustrated in FIG. 3 may be
employed on a limited basis, such as only during the presence of the signal of interest for example, or may be employed continuously. In other words, the method specifically illustrated in FIG. 3 may be employed in a continuous loop type fashion, either
for a limited or extended period of time. In either case, the error power of the input is estimated over time, and fidelity metrics are determined (each using one or more error power estimates of the input) and used to decode the input over time.
FIG. 4 illustrates a flow diagram of another embodiment of a method that may be performed using the system of FIG. 2, in accordance with one embodiment of the present invention. In one embodiment, the error power of an input to the system is
estimated as illustrated by block 401. A fidelity metric is determined, using the error power estimate as illustrated by block 403. The determined fidelity metric is then saved for future use in communications as illustrated by block 405. Like the
method illustrated in FIG. 3, the method illustrated in FIG. 4 may be employed on a limited basis, such as only during time periods when no signal of interest is present, for example, or may be employed continuously. In other words, the method
specifically identified in FIG. 4 may, like that method illustrated in FIG. 3, be employed in a continuous loop type fashion, for a limited or extended period of time. In either case, the error power of the input is estimated over time, fidelity metrics
are determined (each using one or more error power estimates of the input) and information about the fidelity metrics stored for future use in communications.
Specifically, the stored information about the fidelity metrics may be used in transmit waveform optimization for example. In other words, the information may be used to determine a waveform that best suits the communication channel given what
has been learned about the channel over time, as reflected in the stored fidelity metrics. The stored information about the fidelity metrics may also (or alternatively) be used in selecting receiver algorithms that are robust given the limitations of
the channel, again as reflected in the stored fidelity metrics. Additional detail regarding use of catalogued channel fidelity metric information for future communications is provided below.
In one embodiment of the present invention, the methods discussed above with respect to FIGS. 3 and 4 may be used in conjunction. For example, the method of FIG. 3 may be employed when a signal of interest is present, while the method of FIG. 4
may be used when a signal of interest is not present.
The error power estimates provided previously with respect to FIGS. 2-4 may be generated in a number of ways, in the presence or absence of a signal of interest. In the absence of a signal of interest, the input power to the receiver may simply
be the noise power. Filtering to the bandwidth of the signal of interest may be used if desirable.
In an embodiment where the communication system (similar to the system of FIG. 2) is a digital communications system, one particular method for gathering the error power estimates during signaling is to calculate the distance (squared, for power)
between the received signal and the nearest constellation point in the digital system's signaling alphabet. This error vector is typically available or readily obtainable from a slicer in a digital communications receiver.
The length of sliding window 205 of FIG. 2 is important in its selection and application, but in general, may be any length. A shorter window is a subset of a longer window, so longer and longer windows may theoretically provide better and
better channel fidelity metrics. However, in practice, the window length should, for example: (1) be sized to accommodate a given (tolerable) amount of delay (acceptable to the rest of the receiver processing) in generating the channel fidelity metric;
(2) not unnecessarily increase the complexity of the overall receiver; and (3) account for the durations or dynamics expected, or previously observed, in the dominating channel impairments. For example, if transitory channel impairment has a duration of
up to 10 symbols in a given digital communications system, then it is hard to justify the use of a window of 100 symbols. Similarly, a window of only 4 symbols, with the expectation of a persistence of 10 symbols of a given impairment condition,
needlessly lessens the ability of the fidelity processor to make the best channel fidelity assessment, as it is denied relevant (correlated) information regarding the channel fidelity.
Many forms are contemplated for processing the sequence of error power estimates in the fidelity processor 207 of FIG. 2, which forms may depend on: (1) the complexity allowed; (2) the size of the sliding window or duration or persistence of the
impairment states; (3) the delay allowed in generating the channel fidelity metrics; and (4) on the use of the channel fidelity metric (i.e., the accuracy of the metric in matching the impairment level).
In its most simple form, the fidelity processor 207 may simply compare each error power estimate against a threshold, and output a binary channel fidelity estimate--i.e., "channel OK," and "channel degraded." While the window in this case
consists of a single sample (or a single symbol in the digital communications example), the use of the catalogue of this information, and the beneficial use of this metric in subsequent receiver processing, may be employed in one embodiment of the
present invention (such as shown in FIG. 2 and discussed with respect to FIGS. 3 and 4, for example).
FIG. 5A illustrates a flow diagram of a method of impairment mitigation in accordance with one specific embodiment of the present invention, for use in connection with digital communications. First, a symbol (or set of symbols) is received as
illustrated by block 501A, and the closest constellation point to each of the symbols is determined as illustrated by block 503A. As provided previously, the closest constellation point may be determined from a slicer in the receiver.
Next, the error power of the symbols is calculated using, for example, the square of the distance between the received signal and the nearest constellation point in the digital system's signaling alphabet, also as provided previously and as
illustrated by block 505A. The sum of the error power of all the symbols is then compared to a threshold of error power as illustrated by block 507A. This is performed, for example, in the fidelity processor. If it is determined that the error power
is greater than the threshold, it is assumed that the channel is degraded, and all the symbols are erased as illustrated by block 509A. If instead it is determined that the calculated error power of the symbols is not above the threshold (i.e., less
than the threshold), it is assumed that the channel is OK, and the symbols are kept as illustrated by block 511A. In either case, the decision is communicated to the decoder as illustrated by block 513A. In other words, if the symbol is kept as
illustrated by block 51 IA, the symbol is simply communicated to the decoder as illustrated by block 513A, whereas if the symbol is erased as illustrated by block 509A, an indication that the symbol has been erased is communicated to the decoder as
illustrated by block 513A. This process is repeated for each set of symbols received.
While the method illustrated in FIG. 5A is performed on multiple symbols, it is contemplated that a subset of sy | | |
