An MOS-type solid-state imaging apparatus includes an imaging region formed by two-dimensionally arranging unit cells serving as photoelectric conversion portions on a semiconductor substrate, a plurality of vertical address lines arranged in a row direction of the imaging region to select a row of unit cells to be addressed, a plurality of vertical signal lines arranged in a column direction of the imaging region to read out signals from the unit cells in each column, a plurality of load transistors each connected to one end of each of the vertical signal lines, and a plurality of horizontal selection transistors each connected to the other end of each of the vertical signal lines. In this apparatus, each unit cell includes a photodiode serving as a photoelectric conversion portion, an amplification transistor having a gate to which an output from the photodiode is supplied, and a source and a drain respectively connected to the vertical signal line and the vertical address line, an address capacitor connected between the gate of the amplification transistor and the vertical address line, and a reset transistor connected in parallel with the address capacitor.
CROSS-REFERENCE TO RELATED DOCUMENTS
The present patent document is a divisional of U.S. application Ser. No. 09/733,917 filed on Dec. 12, 2000, which is a divisional of U.S. application Ser. No. 09/022,124, filed on Feb. 11, 1998, now U.S. Pat. No. 6,239,839, which is a continuation application of Application No. PCT/JP96/02280, filed on Aug. 12, 1996, now abandoned; and in turn claims priority to JP 7-206140, JP 7-206143, JP 7-206144 filed on Aug. 11, 1995, and JP 8-059845, filed on Mar. 15, 1996, the entire contents of each of which are hereby incorporated herein by reference.
Priority Data
Aug 11, 1995 [JP] 7-206140 Aug 11, 1995 [JP] 7-206143 Aug 11, 1995 [JP] 7-206144 Mar 15, 1996 [JP] 8-059845
