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Cascode connection circuit
   
Document Number
US Patent 7378912
Issued Date
May 27, 2008
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Abstract
A cascode connection circuit includes a first field effect transistor (FET) which has a source terminal and a drain terminal, the source terminal being connected to ground; a second FET which has a source terminal and a gate terminal, the source terminal being connected to the drain terminal of the first FET; and a first resistor and a first capacitor connected in series between the source terminal of the first FET and the gate terminal of the second FET. The first FET and the second FET are cascode-connected to each other. The product of the resistance of the first resistor and the capacitance of the first capacitor does not exceed 0.1 times the period of an operating frequency of the circuit.
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Number of Claims:
10
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Published
May 27, 2008
Application Number
11/437,678
Filed
May 22, 2006
US Classification
330/311  
Int'l Classification
H03F   1/22   (20060101)  
Attorney/Law Firm
Priority Data
Aug 26, 2005 [JP] 2005-245251
USPTO Field of Search
330/302   330/311  
Related Patents
7489201 - Millimeter-wave cascode amplifier gain boosting technique - Owned by Georgia Tech Research Corp. (Atlanta, GA)

Disclosed is a gain boosting technique for use with millimeter-wave cascode amplifiers. The exemplary technique may be implemented using a 0.18 .mu.m SiGe process (F.sub.T=140 GHz). It has also been shown that the technique is effective for CMOS processes with comparable F.sub.T. An exemplary gain-enhanced cascode stage was measured to have higher than 9 dB gain with a 1-dB bandwidth above 6 GHz with a DC power consumption of 13 mW. In addition, one cascode stage without gain boosting may be cascaded with two gain-boosted cascode amplifier stages to implement a three-stage LNA. The measured stable gain is higher than 24 dB at 60 GHz with a 3-dB bandwidth of 3.1 GHz for 25 mW of DC power consumption. It is believed that this is the first 60 GHz LNA with a higher than 20 dB gain using a 0.18 .mu.m SiGe process.

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