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Image sensor, driving method and camera
 
   
Document Number
US Patent 7379108
Issued Date
May 27, 2008
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Abstract
The image sensor according to the present invention comprises a shift register which includes a plurality of stages of unit registers Res, a plurality of transistors Tr3, and a plurality of transistors Tr8; each transistor Tr3 corresponds to one of the unit registers Res, and resets an input signal In of a back unit register when the corresponding unit register Res to the Tr3 outputs a high level signal, the back unit register being arranged in back of the corresponding unit register Res in shifting direction; and each transistor Tr8 corresponds to one of the unit registers, and resets an input signal of the front unit register when the corresponding unit register to the Tr8 outputs a high level signal, the front unit register being arranged in front of the corresponding unit register in shifting direction.
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Number of Claims:
10
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Published
May 27, 2008
Application Number
10/802,939
Filed
March 18, 2004
US Classification
348/302   348/E3.019 348/E3.029
Int'l Classification
H04N   3/14   (20060101)   H04N   5/335   (20060101)  
Priority Data
Mar 19, 2003 [JP] 2003-075769
USPTO Field of Search
348/302  
Related Patents
7564442 - Shift register, and solid state image sensor and camera using shift register - Owned by Canon Kabushiki Kaisha (Tokyo,JP)

The present invention provides a solid state image sensor and a camera using such a solid state image sensor, in which all of stage registers of the shift register can be reset efficiently without increasing the number of pads and/or sensor pins. The solid state image sensor comprises a plurality of photoelectric conversion elements 31 arranged in a two-dimensional array, a vertical shift register 503 disposed in a column direction and a horizontal shift register 504 disposed in a row direction and is characterized in that a timing for controlling resetting means for a first stage register of the shift register differs from a timing for controlling a second stage register and subsequent stage registers. Further, as a concrete example, the second stage register and subsequent stage registers are rest by a pulse for driving the shift register and the first stage register is reset by a pulse in which a high level is reached only upon power ON.

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