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Method of forming dual interconnects in manufacturing MRAM cells
 
   
Document Number
US Patent 7381574
Issued Date
June 3, 2008
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Inventors
Kim; Woosik (Boissettes,FR)
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Abstract
A method of forming dual interconnects in a magnetoresistive memory cell includes: providing an intermediate product including: a metallization layer including metallic lines; a magnetoresistive junction element conductively connected to a first of the metallic lines by a via through a first non-conductive layer; a metallic hard mask disposed on the magnetoresistive junction element; a second non-conductive layer above the first non-conductive layer in regions over the hard mask and a second of the metallic lines; a third non-conductive layer disposed above the hard mask; and a fourth non-conductive layer disposed on the third non-conductive layer. The method further includes partially opening first and second trenches to uncover the second non-conductive layer above the hard mask and second metallic line, respectively; fully opening the first and second trenches to uncover the hard mask and second metallic line, respectively; and filling the first and second trenches with conductive material.
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Number of Claims:
8
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Owner
Altis Semiconductor (Corbeil Essonnes Cedex,FR)
Published
June 3, 2008
Application Number
11/289,787
Filed
November 30, 2005
US Classification
438/3   438/618
Int'l Classification
H01L   21/00   (20060101)  
Examiner
Attorney/Law Firm
USPTO Field of Search
438/3   438/618  
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