An integrated circuit structure includes a digit line and an electrode adapted to be part of a storage cell capacitor and includes a barrier layer interposed between a conductive plug and an oxidation resistant layer. An insulative layer protects sidewalls of the barrier layer during deposition and anneal of a dielectric layer. The method includes forming the conductive plug recessed in an insulative layer. The barrier layer is formed in the recess and the top layer. An oxidation resistant conductive layer and a further oxide layer are formed in the recess. The conductive layer is planarized to expose the oxide or oxide/nitride layer. The oxide layers are then etched to expose the top surface and vertical portions of the conductive layer. A dielectric layer is formed to overlie the storage node electrode. A cell plate electrode is fabricated to overlie the dielectric layer.
This is a Divisional of application Ser. No. 10/939,928, filed Sep. 13, 2004, now U.S. Pat. No. 7,153,707, which is a Continuation of application Ser. No. 09/489,954, filed Jan. 24, 2000, now U.S. Pat. No. 6,791,131, which is a Divisional of application Ser. No. 08/572,392, filed Dec. 14, 1995, now U.S. Pat. No. 6,030,847, which is a Continuation-In-Part of application Ser. No. 08/390,336 filed on Feb. 17, 1995, now U.S. Pat. No. 5,478,772 which is a continuation of Ser. No. 08/044,331 filed on Apr. 2, 1993, now abandoned.
A continuation of Ser. No. 08/313,677 filed on Sep. 27, 1994, now U.S. Pat. No. 5,506,166 which is a divisional of Ser. No. 08/104,525 filed on Aug. 10, 1993, now U.S. Pat. No. 5,381,302 and which may contain similar material. All of the above applications are incorporated herein by reference.
