A memory test circuit receives test pattern data from a processing unit having a first data width, expands the test pattern to a second data width greater than the first data width, and writes the expanded test pattern data into a memory having the second data width, thereby avoiding the need for extra write cycles when a processing unit tests a memory having a greater data width. The test pattern data may be expanded by, for example, copying a specific bit to multiple bit positions, inverting a specific bit and copying the inverted bit to multiple bit positions, or performing arithmetic operations that generate a test pattern similar to the test pattern received from the processing unit.
