or
Bookmark and Share
Method to reduce soft error rate in semiconductor memory
   
Document Number
US Patent 7389446
Issued Date
June 17, 2008
Link
Inventors
Map
Abstract
A method for reducing soft error rates in semiconductor memory. In one embodiment, memory is partitioned into a) boot and download memory, b) program memory and c) data memory. Each partition receives protection according to the importance of the data stored. The boot memory is protected by sensing errors and repairing them utilizing on-chip data storage redundancy and exchange. The program memory is protected by sensing errors and repairing damaged data by reloading it using the program stored in the boot and download memory. The data memory is selectively protected similar to the program memory, but with the added feature of regular saving to disk from which to check for accurate data in the event of corruption. In another embodiment, any or all of the soft error protection features are selectable on a global basis, a memory type basis or, in the cases of program and data memory, on a block level basis.
Tags:
Description:
Amusing 0%
Clever 0%
Complex 0%
Efficient 0%
Historic 0%
Important 0%
Innovative 0%
Interesting 0%
Practical 0%
Simple 0%
Number of Claims:
13
Comments:
no comments yet
Owner
Published
June 17, 2008
Application Number
10/919,212
Filed
August 16, 2004
US Classification
714/42  
Int'l Classification
G06F   11/00   (20060101)  
USPTO Field of Search
714/42  
Related Patents
Claims
Description
About| FAQs| Terms & Disclaimer| Link to Us| Contact Us