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Integrated circuit with integrated debugging mechanism for standard interface
   
Document Number
US Patent 7395454
Issued Date
July 1, 2008
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Inventors
Avivi; Amit (Sunnyvale, CA)
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Abstract
A circuit having a corresponding method comprises one or more circuits each to produce one or more status signals, wherein each of the status signals represents a status of a respective one of the one or more circuits; a memory; a memory controller to store a plurality of samples of the one or more status signals in the memory; a plurality of input/output terminals; an interface in communication with one or more of the input/output terminals; and a debug circuit to transfer the one or more samples of the status signals from the memory to the interface.
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Number of Claims:
44
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Owner
Published
July 1, 2008
Application Number
11/028,687
Filed
January 4, 2005
US Classification
714/30  
Int'l Classification
G06F   11/00   (20060101)  
Examiner
USPTO Field of Search
714/30  
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