A methodology for generating scan based transition patterns (i.e., ATPG pattern generation for transition delay faults ("TDF")) wherein when either a slow-to-rise (STR) or a slow-to-fall (STF) transition fault is detected, that specific fault is removed from a fault universe as well as its companion TDF, wherein the companion fault is a fault on the same node as the detected fault but has the opposite transition. In other words, if a slow-to-rise (STR) transition fault is detected, the slow-to-rise (STR) transition fault is removed from the fault universe as well as its corresponding slow-to-fall (STF) transition fault (and vise versa). By removing companion faults as well as those which are specifically detected, pattern generation run time is reduced as well as the total pattern count for the final delay test pattern.
RELATED APPLICATION (PRIORITY CLAIM)
This patent application is a continuation of U.S. patent application Ser. No. 10/900,224, filed on Jul. 27, 2004 now U.S. Pat. No. 7,216,280, which claims the benefit of U.S. Provisional Application Ser. No. 60/564,102, filed Apr. 20, 2004 and which is hereby incorporated herein by reference in its entirety.
