System and method for automatic fault-testing of a logic block and the interfaces of macros with logic gates inside a chip, using an at-speed logic-BIST internal to the chip. Following an initialization of internal storage elements, a set of test signals are generated and processed by the logic block. The output of the logic block is accumulated into a signature and compared to a reference signature to detect faults. Testing can be performed on an ATE (Automatic Test Equipment) using a simple test vector, or can be performed by a field engineer on the actual board comprising the chip.
RELATED APPLICATIONS
This patent application takes priority under 35 U.S.C. 119(e) to U.S. Provisional Patent Application No. 60/619,201 filed on Oct. 15, 2004 entitled "AUTOMATIC FAULT TESTING OF A VIDEO DECODER PORTION OF AN ASIC BY INTERNAL AT-SPEED LOGIC-BIST" by Mushirabad et al, which is incorporated by reference in its entirety.
