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Loop-back method for measuring the interface timing of semiconductor devices with the aid of signatures and/or parity methods
   
Document Number
US Patent 7398444
Issued Date
July 8, 2008
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Abstract
The invention relates to a method for testing a memory device with the memory device being able to be operated in a normal operating mode and a test mode and encompassing an output driver, input driver, and data pads. The method includes the steps of communicating test input data to be used for a test to the memory device, performing a test using the test input data in order to obtain test output data, the test data read out being passed via an output driver, at least one data pad, and an input driver, wherein the input drivers and output drivers are switched during the test in such a way as to enable data to be simultaneously read from and written to the memory device, and creating a data test result from the test output data. Furthermore, the invention relates to a memory device and a system for testing a memory device.
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Number of Claims:
24
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Published
July 8, 2008
Application Number
11/220,332
Filed
September 6, 2005
US Classification
714/736  
Int'l Classification
G01R   31/28   (20060101)  
Attorney/Law Firm
Priority Data
Sep 06, 2004 [DE] 10 2004 043 050
USPTO Field of Search
714/736  
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