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Pipelining D states for MRU steerage during MRU/LRU member allocation
   
Document Number
US Patent 7401189
Issued Date
July 15, 2008
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Abstract
A method and apparatus for preventing selection of Deleted (D) members as an LRU victim during LRU victim selection. During each cache access targeting the particular congruence class, the deleted cache line is identified from information in the cache directory. A location of a deleted cache line is pipelined through the cache architecture during LRU victim selection. The information is latched and then passed to MRU vector generation logic. An MRU vector is generated and passed to the MRU update logic, which is selects/tags the deleted member as a MRU member. The make MRU operation affects only the lower level LRU state bits arranged in a tree-based structure state bits so that the make MRU operation only negates selection of the specific member in the D state, without affecting LRU victim selection of the other members.
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Number of Claims:
5
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Published
July 15, 2008
Application Number
11/054,067
Filed
February 9, 2005
US Classification
711/140   711/136 711/E12.021 711/E12.072 711/E12.075
Int'l Classification
G06F   12/00   (20060101)   G06F   13/00   (20060101)   G06F   13/28   (20060101)  
Assistant Examiner
USPTO Field of Search
711/140   711/136  
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