Generation of jittered sub-pixel samples using programmable sub-pixel offsets

Claims

The invention claimed is:

1. A programmable graphics processor for generating anti-aliased images utilizing a non-periodic jitter pattern that varies from pixel to pixel, comprising: a storage element configured to store programmed sub-pixel offset values, wherein the number of sub-pixel offset values stored is dependent on the resolution of the image to be displayed; an offset access unit coupled to the storage element, the offset access unit configured to read a portion of the sub-pixel offset values based on at least a portion of the coordinates of a pixel position; a sample computation unit configured to combine the pixel position and the portion of the programmed sub-pixel offset values, read from the storage element, dependent on the resolution of the image to be displayed to produce a jittered sub-pixel sample position for each and every sub-pixel sample cell within each pixel of an antialiased image so that the jitter pattern is effectively non-periodic, but is antialiased consistently from frame to frame, each sub-pixel offset value being either added to or subtracted from the pixel position coordinate to establish the sub-pixel sample position based on whether the sub-pixel sample position is in the left or right half of the cell; a rasterizer configured to produce sub-pixel coverage data associated with a fragment using the jittered sub-pixel sample positions; a shader configured to compute a depth value corresponding to the fragment depth at the pixel position; and a raster operations unit configured to produce sub-pixel depth values using the depth value corresponding to the fragment depth at the pixel position and the jittered sub-pixel sample positions.

2. The programmable graphics processor of claim 1, wherein the offset access unit reads the portion of the sub-pixel offset values using at least a portion of the pixel position.

3. The programmable graphics processor of claim 1, wherein the sub-pixel offset value is either added to or subtracted from the pixel position coordinate to establish the sub-pixel sample position based on whether the sub-pixel sample position is in the left or right half of the cell.

4. The programmable graphics processor of claim 1, wherein the storage element contains an odd number of sub-pixel offset values so that the same offset value may be used for both horizontal and vertical offset.

5. The programmable graphics processor of claim 1, further comprising a software driver configured to restrict the programmed sub-pixel offset values to those which will result in sub-pixel sample positions that are within the boundary of a pixel associated with the pixel position.

6. The programmable graphics processor of claim 1, wherein the raster operations unit is configured to process the sub-pixel depth values within the fragment as indicated by the sub-pixel coverage data.

7. The programmable graphics processor of claim 1, wherein the shader is configured to compute a color value corresponding to the fragment.

8. The programmable graphics processor of claim 7, wherein the color value corresponds to the fragment color at the pixel position.

9. The programmable graphics processor of claim 7, wherein the color value corresponds to the fragment color at another pixel position within the fragment when the pixel position does not lie within the fragment.

10. The programmable graphics processor of claim 1, wherein a single programmed sub-pixel offset value is combined with both an X coordinate and a Y coordinate of the pixel position to produce the jittered sub-pixel sample positions.

11. The programmable graphics processor of claim 1, wherein the sample computation unit is further configured to combine the pixel position and the portion of the programmed sub-pixel offset values by adding a first programmed sub-pixel offset value to a Y coordinate of the pixel position when the sub-pixel sample cell is located in an upper half of the pixel.

12. The programmable graphics processor of claim 1, wherein the sample computation unit is further configured to combine the pixel position and the portion of the programmed sub-pixel offset values by subtracting a first programmed sub-pixel offset value from a Y coordinate of the pixel position when the sub-pixel sample cell is located in a lower half of the pixel.

13. The programmable graphics processor of claim 1, wherein the sample computation unit is further configured to combine the pixel position and the portion of the programmed sub-pixel offset values by subtracting a first programmed sub-pixel offset value from an X coordinate of the pixel position when the sub-pixel sample cell is located in a left half of the pixel.

14. A method of determining sub-pixel sample positions for a pixel position to reduce aliasing utilizing a non-periodic jitter pattern that varies from pixel to pixel, the method comprising: determining pixel positions for a plurality of pixels in an image; determining a plurality of sub-pixel sample cells for each of the pixels; storing a number of sub-pixel offset values, wherein the number of sub-pixel offset values stored is dependent on the resolution of the image to be displayed; selecting a sub-pixel offset value for each and every one of the sub-pixel sample cells within each of the pixels based on the pixel positions, wherein the stored sub-pixel offset values are accessed using selected bits of the pixel position coordinates; combining the selected sub-pixel offset values with the pixel positions to determine a sub-pixel sample pattern defining the location of each cell of the plurality of sub-pixel sample cells based on the pixel position being sampled, each sub-pixel offset value being either added to or subtracted from the pixel position coordinate to establish the sub-pixel sample position based on whether the sub-pixel sample position is in the left or right half of the cell; and rendering graphics primitives representing the image using the sub-pixel sample pattern to produce an anti-aliased image for display, wherein the sub-pixel sample pattern used is non-periodic so that the jitter pattern is non-periodic, but is antialiased consistently from frame to frame.

15. A method as claimed in claim 14, wherein the sub-pixel offset value is added to a coordinate of the pixel position for sub-pixel sample cells in an upper half or a right half of the pixel.

16. A method as claimed in claim 14, wherein the sub-pixel offset value is applied as both a horizontal and vertical offset to the X,Y pixel position.

17. A method as claimed in claim 14, wherein the sub-pixel offset values are stored in a lookup table having a length dependent on the desired period between use of the offset value.