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Processor having efficient function estimate instructions
   
Document Number
US Patent 7406589
Issued Date
July 29, 2008
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Abstract
High-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instruction is provided for each different function, while only a single interpolation instruction is needed, since the single interpolation instruction can perform the interpolation step for any of the functions to be estimated. Thus, significantly less overhead is incurred than would be incurred with specialized hardware, while still maintaining a uniform FPU latency, which allows for much simpler control logic.
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Number of Claims:
7
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Published
July 29, 2008
Application Number
11/127,848
Filed
May 12, 2005
US Classification
712/222   708/495 708/500 708/502 708/508
Int'l Classification
G06F   7/552   (20060101)   G06F   7/38   (20060101)   G06F   7/544   (20060101)  
Examiner
Assistant Examiner
USPTO Field of Search
712/222   708/495   708/496   708/497   708/498   708/499   708/500   708/501   708/502   708/503   708/504   708/505   708/506   708/507   708/508   708/509   708/510   708/511   708/512   708/513   708/514  
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