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Configuring a portion of a pipeline accelerator to generate pipeline date without a program instruction
   
Document Number
US Patent 7418574
Issued Date
August 26, 2008
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Inventors
Jones; Mark (Centreville, VA)
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Abstract
A peer-vector machine includes a host processor and a hardwired pipeline accelerator. The host processor executes a program, and, in response to the program, generates host data, and the pipeline accelerator generates pipeline data from the host data. Alternatively, the pipeline accelerator generates the pipeline data, and the host processor generates the host data from the pipeline data. Because the peer-vector machine includes both a processor and a pipeline accelerator, it can often process data more efficiently than a machine that includes only processors or only accelerators. For example, one can design the peer-vector machine so that the host processor performs decision-making and non-mathematically intensive operations and the accelerator performs non-decision-making and mathematically intensive operations. By shifting the mathematically intensive operations to the accelerator, the peer-vector machine often can, for a given clock frequency, process data at a speed that surpasses the speed at which a processor-only machine can process the data.
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Number of Claims:
34
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Owner
Published
August 26, 2008
Application Number
10/684,102
Filed
October 9, 2003
US Classification
712/15   712/2 712/34
Int'l Classification
G06F   15/76   (20060101)  
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Parent Case
CLAIM OF PRIORITY This application claims priority to U.S. Provisional Application Ser. No. 60/422,503, filed on Oct. 31, 2002, which is incorporated by reference.
USPTO Field of Search
712/2   712/34   712/15   712/20  
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