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Computer system and fault processing method in computer system
   
Document Number
US Patent 7426662
Issued Date
September 16, 2008
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Abstract
A manager transmits an I/O bus signal to an I/O bus manager in a computer at a predetermined point of time to inform the I/O bus manager of occurrence of an I/O bus fault. The I/O bus manager initializes an I/O bus and then informs a CPU in the computer of the I/O bus fault as an interruption to be processed by an OS operated by the CPU, whereby the OS can acquire the fault information after the interruption even in the case where an I/O bus fault occurs.
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Number of Claims:
4
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Owner
Hitachi, Ltd. (Tokyo,JP)
Published
September 16, 2008
Application Number
11/078,385
Filed
March 14, 2005
US Classification
714/43   714/E11.023
Int'l Classification
G06F   11/00   (20060101)  
Parent Case
This is a continuation application of U.S. Ser. No. 09/622,372, filed Jan. 12, 2001 now U.S. Pat. No. 6,948,100, which was a National Stage of International Application No. PCT/JP99/00836, filed Feb. 24, 1999.
USPTO Field of Search
714/43  
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