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Management of cache memories in a data processing apparatus
   
Document Number
US Patent 7434007
Issued Date
October 7, 2008
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Abstract
The present invention provides a data processing apparatus and method for managing cache memories. The data processing apparatus comprises a processing unit for issuing an access request seeking access to a data value, and a hierarchy of cache memories for storing data values for access by the processing unit. The hierarchy of cache memories comprises at least an n-th level cache memory and n+1-th level cache memory which at least in part employ exclusive behavior with respect to each other. Each cache memory comprises a plurality of cache lines, at least one dirty value being associated with each cache line, and each dirty value being settable to indicate that at least one data value held in the associated cache line is more up-to-date than a corresponding data value stored in a main memory. When employing exclusive behavior, the n-th level cache memory is operable, on eviction of a cache line from the n-th level cache memory to the n+1-th level cache memory, to additionally pass an indication of the at least one associated dirty value from the n-th level cache memory to the n+1-th level cache memory. This has been found to reduce the frequency of evictions of lines from the n+1-th level cache memory when employing exclusive behaviour.
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Number of Claims:
10
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Owner
ARM Limited (Cambridge,GB)
Published
October 7, 2008
Application Number
11/091,929
Filed
March 29, 2005
US Classification
711/144   711/122
Int'l Classification
G06F   12/00   (20060101)  
Examiner
Assistant Examiner
Attorney/Law Firm
USPTO Field of Search
711/144  
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