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Method for improved process latitude by elongated via integration
   
Document Number
US Patent 7439628
Issued Date
October 21, 2008
Link
Inventors
Colburn; Matthew E. (Hopewell Junction, NY)
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Abstract
Interconnect dual damascene structure are fabricated by depositing on a layer of at least one dielectric, a mask forming layer for providing the via-level mask layer of the dual damascene structures; creating an elongated via pattern in the via-level mask layer; depositing a layer of line-level dielectric and creating a line pattern through the layer of line-level dielectric, and transferring the line pattern through the projected intersection of the elongated via-level pattern and of the line-level pattern thereby generating an aligned dual damascene structure. A conductive liner layer is deposited in the dual damascene structure followed by filling the dual damascene structure with a conductive fill metal to form a set of metal lines. The metal and liner layers are planarized.
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Number of Claims:
7
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Published
October 21, 2008
Application Number
11/474,420
Filed
June 26, 2006
US Classification
257/774   257/758 257/E23.145
Int'l Classification
H01L   23/48   (20060101)   H01L   23/52   (20060101)  
Examiner
Attorney/Law Firm
Parent Case
This application is a Divisional Application of U.S. application Ser. No. 10/887,086, filed Jul. 9, 2004, and now U.S. Pat. No. 7,071,097.
USPTO Field of Search
257/758   257/774   257/E23.145  
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