or
Bookmark and Share
   
Document Number
US Patent 7439779
Issued Date
October 21, 2008
Link
Inventors
Map
Abstract
A driver circuit for driving a load (3) connected between an output (FO) of a first channel driver (D1) and an output (RO) of a second channel driver (D2). The first and second channel drivers (D1, D2) each include switch transistors for charging and discharging the gates of upper and lower output transistors in response to a command from an input pulse, a charging/discharging circuit (A2, B2) for determining a charging/discharging speed, and a detector circuit (A1, B1) for detecting a state of the channel driver on the opposite side. A dead time period and a speed of charging/discharging the gates of the upper and lower output transistors are changed according to the state of the channel driver on the opposite side. Thus, it is possible to achieve a channel driver circuit which can prevent a shoot-through current, adjust an output slew rate, and obtain preferred linearity as an input-output characteristic.
Tags:
Description:
Amusing 0%
Clever 0%
Complex 0%
Efficient 0%
Historic 0%
Important 0%
Innovative 0%
Interesting 0%
Practical 0%
Simple 0%
Number of Claims:
6
Comments:
no comments yet
Published
October 21, 2008
Application Number
10/988,661
Filed
November 16, 2004
US Classification
327/112  
Int'l Classification
H03B   1/00   (20060101)   H03K   3/00   (20060101)  
Examiner
Attorney/Law Firm
Priority Data
Nov 21, 2003 [JP] 2003-391537
USPTO Field of Search
327/108   327/110   327/112  
Related Patents
Claims
Description
About| FAQs| Terms & Disclaimer| Link to Us| Contact Us