There is provided a testing apparatus including: a pattern generator that generates an address signal and a data signal to be supplied to a plurality of memories under test and an expectation signal; a plurality of logic comparators that generate fail data when an output signal output from the plurality of memories under test and the expectation signal are not identical with each other; a plurality of fail memories that store the fail data generated from the plurality of logic comparators; a plurality of memory controllers that generate bad address information showing a bad address in the memory under test based on the fail data stored on the plurality of fail memories; a plurality of universal buffer memories that store the bad address information generated from the plurality of memory controllers; and a plurality of bad information writing sections that concurrently write bad information into the bad address in the plurality of memories under test, which is shown by the bad address information stored on the plurality of universal buffer memories.
CROSS REFERENCE TO RELATED APPLICATION
This is a continuation application of PCT/JP2005/005171 filed on Mar. 22, 2005 which claims priority from a Japanese Patent Application NO. 2004-87924 filed on Mar. 24, 2004, the contents of which are incorporated herein by reference.
The present invention relates to a DRAM stacked packages, a DIMM, a method for testing them, and a semiconductor manufacturing method. According to the present invention, there is provided a DRAM stacked package comprising: a plurality of stacked DRAMs; external terminals to which test equipment is connected, said external terminals being used to input/output at least address, command, and data; and an interface chip provided between said plurality of stacked DRAMs and said external terminals. The plurality of DRAMs and the interface chip are implemented on a package. The interface chip comprises: a test circuit including: an algorithmic pattern generator for generating a test pattern used to test the plurality of DRAMs; applying circuits for applying said generated test pattern to the plurality of DRAMs; and a comparator for comparing each response signal received from the plurality of DRAMs with an expected value for judgment.
