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Imager pixel with capacitance for boosting reset voltage
   
Document Number
US Patent 7446807
Issued Date
November 4, 2008
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Abstract
A pixel cell in which a capacitance is coupled between a storage node and a row select transistor and another capacitance is coupled between a storage node and a voltage supply or ground source potential to boost a reset voltage.
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Number of Claims:
39
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Owner
Published
November 4, 2008
Application Number
11/002,281
Filed
December 3, 2004
US Classification
348/308  
Int'l Classification
H04N   5/335   (20060101)  
Examiner
Assistant Examiner
Attorney/Law Firm
USPTO Field of Search
348/308   348/312   348/313   348/314  
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7511275 - Semiconductor device, and control method and device for driving unit component of semiconductor device - Owned by Sony Corporation (Tokyo,JP)

A solid-state imaging device, such as a CMOS sensor, includes a unit pixel having a charge generation unit for generating signal charge, a floating diffusion for accumulating the signal charge generated by the charge generation unit, a transfer gate transistor for transferring the signal charge in the charge generation unit to the floating diffusion, a reset transistor for resetting the floating diffusion, and an amplifying transistor for generating a signal in accordance with the signal charge generated by the charge generation unit and outputting the signal to a vertical signal line. The width of a reset pulse for driving the reset transistor is sufficiently decreased to, for example, less than or equal to 1/2, and preferably less than or equal to 1/5 of the response time of a signal that has occurred on the vertical signal line in response to the reset pulse.

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