Peripheral input and output buffer circuitry is tested using scan path circuitry selectively connecting external signals TSA, TSB, and TSC to the buffer circuitry. This is in addition to testing the internal circuitry of the integrated circuit with the scan path circuitry. An external signal, TSC, provides a load to the output of the buffer circuitry. An external signal, TSA, receives a response from input buffer circuitry and supplies a stimulus signal to output buffer circuitry. An external signal, TSB, receives a response signal from output buffer circuitry and supplies a stimulus signal to input buffer circuitry. This avoids a wafer tester having to contact bond pads connected to the buffer circuitry.
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a divisional of application Ser. No. 10/806,539, filed Mar. 23, 2004, now U.S. Pat. No. 7,257,749, issued Aug. 14, 2007;
Which was a divisional of application Ser. No. 09/745,523, filed Dec. 21, 2000, now U.S. Pat. No. 6,731,106, issued May 4, 2004;
Which was a divisional of application Ser. No. 09/049,626, filed Mar. 27, 1998, now U.S. Pat. No. 6,199,182, issued Mar. 6, 2001;
Which claimed priority from Provisional Application No. 60/041,729, filed Mar. 27, 1997.
