Aspects of the invention may include testing and debugging an embedded device under test. Testing and debugging and embedded device under test may include the step of loading an instruction into a parameterized shift register of each one of a plurality of BIST modules coupled to an individual one of a plurality of embedded memory modules comprising the embedded device under test. An identity of each of the instruction loaded into the parameterized shift register of each one of the plurality of BIST modules may subsequently be determined. A separate test signal may be generated from each one of the plurality of BIST modules corresponding to the determined identity of the instruction loaded in each one of the plurality of BIST modules, each one of the generated test signals causing control and execution of the testing and debugging of a corresponding one of each of the plurality of embedded memory modules comprising the embedded device under test.
