In an integrated circuit device, element power supply lines connected to a circuit containing a plurality of cells, element ground lines connected thereto, a trunk power supply line connected to each of the element power supply lines, and a trunk ground line connected to each of the element ground lines are provided in a first wiring layer. A branch power supply line connected to the trunk power supply line and a branch ground line connected to the trunk ground line are provided in an upper wiring layer located above the first wiring layer. A wiring structure is determined based on a wiring structure equation expressing the relations among a voltage drop in the lines, the area occupied thereby, and a current consumed thereby and on a circuit characteristic equation expressing, when the circuit is subdivided while the ratio between the area of the circuit and a current consumed thereby is held constant, the relation between an area occupied by a circuit resulting from subdivision and a current consumed thereby.
RELATED APPLICATIONS
This application is a divisional of U.S. patent application Ser. No. 10/879,754 filed Jun. 30, 2004, U.S. Pat. No. 7,155,684, which is a continuation of U.S. patent application Ser. No. 10/084,978 filed Mar. 1, 2002, U.S. Pat. No. 6,794,674, which is based on Japanese Patent Application No. JP 2001-060090 filed Mar. 5, 2001, the contents of which are hereby incorporated by reference in their entirety.
