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Interconnect with high aspect ratio plugged vias
 
   
Document Number
US Patent 7470619
Issued Date
December 30, 2008
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Inventors
Lawyer; Philip H. (Thousand Oaks, CA)
Sokolich; Marko (Los Angeles, CA)
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Abstract
Described is a method for forming a stackable interconnect. The interconnect is formed by depositing a first contact on a substrate; depositing a seed layer (SL) on the substrate; depositing a metal mask layer (MML) on the SL; depositing a bottom anti-reflection coating (BARC) on the MML; forming a photoresist layer (PR) on the BARC; removing a portion of the PR; etching the BARC and the MML to expose the SL; plating the exposed SL to form a first plated plug; removing the layers to expose the SL; removing an unplated portion of the SL; depositing an inter layer dielectric (ILD) on the interconnect; etching back the ILD to expose the first plated plug; and depositing a second contact on the first plated plug. Using the procedures described above, a second plated plug is then formed on the first plated plug to form the stackable plugged via interconnect.
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Number of Claims:
30
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Owner
Published
December 30, 2008
Application Number
11/607,494
Filed
December 1, 2006
US Classification
438/675   257/E21.175 257/E21.586 257/E23.141 438/618 438/631 438/652 438/674 438/678
Int'l Classification
H01L   21/44   (20060101)   H01L   21/4763   (20060101)  
Examiner
Assistant Examiner
USPTO Field of Search
438/618   438/621   438/652   438/674   438/678   257/E21.175   257/E23.021   257/E21.586  
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