Embodiments of methods in accordance with the present invention provide three-dimensional carbon nanotube (CNT) integrated circuits comprising layers of arrays of CNT's separated by dielectric layers with conductive traces formed within the dielectric layers to electrically interconnect individual CNT's. The methods to fabricate three-dimensional carbon nanotube FET integrated circuits include the selective deposition of carbon nanotubes onto catalysts selectively formed on a conductive layer at the bottom of openings in a dielectric layer. The openings in the dielectric layer are formed using suitable techniques, such as, but not limited to, dielectric etching, and the formation of ring gate electrodes, including spacers, that provide openings for depositing self-aligned carbon nanotube semiconductor channels.
CROSS-REFERENCES TO RELATED APPLICATIONS
This application is a divisional application of U.S. application Ser. No. 11/048,231 filed Feb. 01, 2005, and entitled "Microcircuit Fabrication and Interconnection," which is hereby incorporated by reference in its entirety. U.S. application Ser. No. 11/048,231 is a divisional application of U.S. application Ser. No. 10/336,236 filed Jan. 02, 2003, which is also hereby incorporated by reference in its entirety.
