A shift register includes a control unit, a signal switching unit and a buffer unit. The control unit determines whether to transfer an input signal from a first input terminal to a first output terminal according to a first control signal, and determines whether to conduct a first pre-defined voltage to a second output terminal according to a second control signal. The signal switching unit uses the signal output from the first output terminal as one of the considerations for determining whether to conduct a second pre-defined voltage to a third output terminal, and uses the second control signal as one of the considerations for determining whether to conduct the second pre-defined voltage to the first output terminal. The buffer unit outputs signal according to the signals from the first/third output terminals. Further, at least once, the second control signal is enabled after the first control signal has been enabled.
