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Operational amplifier circuit
 
   
Document Number
US Patent 7474152
Issued Date
January 6, 2009
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Abstract
An operational amplifier circuit has a differential input circuit including a first transistor, which receives a first input signal and generates a first voltage, and a second transistor, which receives a second input signal and generates a second voltage. An output stage circuit includes a third transistor responsive to the second voltage, a fourth transistor connected to the third transistor, a fifth transistor responsive to the first voltage, and a sixth transistor connected to the fifth transistor. The output stage circuit generates an output signal of the amplifier circuit at a first node between the fifth and sixth transistors. A seventh transistor connected between the third and fourth transistors controls the potential at a second node between the third and seventh transistors to be the same as the potential of the first input signal in correspondence with the first input signal.
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Number of Claims:
14
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Owner
Fujitsu Limited (Kawasaki,JP)
Published
January 6, 2009
Application Number
11/715,329
Filed
March 8, 2007
US Classification
330/255  
Int'l Classification
H03F   3/26   (20060101)   H03F   3/45   (20060101)  
Attorney/Law Firm
Priority Data
May 26, 2006 [JP] 2006-147469
USPTO Field of Search
330/255   330/265   330/267  
Related Patents
7551030 - Two-stage operational amplifier with class AB output stage - Owned by Samsung Electronics Co., Ltd. (Suwon-si,KR)

An operational amplifier includes a differential amplifier including an active load, a current mirror including a first branch and a second branch, a first switch connected between a first power source and an output node and switched in response to a voltage of a first output terminal of the differential amplifier, a first bias circuit to control an amount of a reference current flowing in the first branch in response to a voltage of a second output terminal of the differential amplifier, a second bias circuit to control a voltage of the second branch in which a mirror current flows, in response to a voltage of the first output terminal, a second switch connected between the output node and a second power source and switched in response to a voltage of the second branch, and a capacitor connected between the output node and the first output terminal.

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