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Comparator architecture
   
Document Number
US Patent 7479915
Issued Date
January 20, 2009
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Abstract
A comparator presents a linear load to input signals when providing a comparison output of two input signals. The comparator contains a transistor configured in a source/emitter follower configuration, and operates in the saturation region for substantially the entire range of strengths of the input signals. As a result, the comparator presents a substantially constant load to the input signals. When incorporated in circuits such as a pipeline ADC, the comparator may substantially eliminate errors due to non-linear loads.
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Number of Claims:
16
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Published
January 20, 2009
Application Number
11/959,494
Filed
December 19, 2007
US Classification
341/161   318/729 326/93 327/536
Int'l Classification
H03M   1/38   (20060101)  
Examiner
USPTO Field of Search
341/139   341/140   341/141   341/142   341/143   341/144   341/145   341/146   341/147   341/148   341/149   341/150   341/151   341/152   341/153   341/154   341/155   341/156   341/157   341/158   341/159   341/160   341/161   341/162   341/163   341/164   341/165   318/729   326/93   327/536  
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