A processor core adopts a pipeline processing method and has an interlock mechanism. A built-in accelerator executes a specific processing in place of the processor core. When a processing is executed by the built-in accelerator and there is no processing to be executed by the processor core, the interlock mechanism stops and restarts the pipeline processing in response to a start of processing and a processing completion of the built-in accelerator, respectively. A processing-completion waiting operation to the built-in accelerator is implemented by using the interlock mechanism, and thus useless power consumption of the processor core during the processing of the built-in accelerator can be easily reduced.
