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Method of forming metal line stacking structure in semiconductor device
   
Document Number
US Patent 7485577
Issued Date
February 3, 2009
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Abstract
The method for forming a metal line stacking structure according to a preferred embodiment of the present invention comprises: sequentially forming a first barrier metal and a first metal layer on a lower dielectric layer that is disposed over a semiconductor substrate, and performing a plasma treatment; forming a second barrier metal on the plasma-treated first metal layer; selectively etching the second barrier metal, the first metal layer, and the first barrier metal to form a metal line layer including the second barrier metal, the first metal layer, and the first barrier metal, which respectively have a predetermined width; and sintering the metal line layer to raise a reaction between the first metal layer and the second barrier metal, thereby generating a metal compound layer.
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Number of Claims:
17
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Owner
Dongbuanam Semiconductor, Inc. (Daechi-Dong, Kangnam-Ku Seoul,KR)
Published
February 3, 2009
Application Number
11/557,306
Filed
November 7, 2006
US Classification
438/675   257/E21.582
Int'l Classification
H01L   21/44   (20060101)  
Examiner
Attorney/Law Firm
Parent Case
CROSS-REFERENCE OF RELATED APPLICATIONS This application is a continuation of U.S. patent application Ser. No. 10/418,791, filed on Apr. 18, 2003 now U.S Pat No. 7,141,880, which is incorporated herein by reference.
USPTO Field of Search
438/624   438/672   438/675   257/E21.582   257/E21.592  
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