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Circuit for biasing a transistor and related system and method
   
Document Number
US Patent 7486143
Issued Date
February 3, 2009
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Inventors
Rohdin; Hans (Los Altos, CA)
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Abstract
An embodiment of a circuit for biasing a transistor such as an amplifier transistor includes reference and bias nodes, and includes buffer, reference, and feedback stages. The reference node receives a reference current, and the bias node, which is for coupling to the transistor, carries a bias signal. The buffer stage buffers the reference node from the bias node. The reference stage generates the bias signal from the reference current, and the bias signal causes the transistor to conduct a bias current that is proportional to the reference current. And the feedback stage is coupled between the reference and bias nodes. As compared to known bias circuits, such a bias circuit may reduce the amplitude and duration of a transient overshoot in the bias current of a field-effect transistor when the DC component of the transistor's drain voltage transitions from one value to another value. Such a bias circuit may also reduce the difference between the values of the bias current through the transistor for different supply voltages. And such a bias circuit may reduce the difference between the predicted and actual values of the bias current through the transistor for a given input voltage such as that between the gate and the source of a field-effect transistor.
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Number of Claims:
6
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Published
February 3, 2009
Application Number
11/525,759
Filed
September 22, 2006
US Classification
330/296   330/290
Int'l Classification
H03F   3/04   (20060101)  
Examiner
Assistant Examiner
USPTO Field of Search
330/285   330/296   330/288  
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