A multi-slice network processor processes a packet in packet slices for transfer over a multi-port network interface such as a switch fabric. The network processor segments a packet into cells having a target size. A group of cells of a common packet form a packet slice which is independently processed by one of a number of parallel processing and storage slices. Load balancing may be used in the selection of processing slices. Furthermore, the network processor may load balance slices across the multi-port network interface to one or more destination slices of another network processor. The multi-slice processor uses post header storage delivery on ingress processing to the multi-port interface thereby reducing temporary storage requirements. The multi-slice network processor may also utilize sequence numbers associated with each packet to ensure that prior to transmission onto a destination network, the packet is in the correct order for a communication flow.
CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of priority under 35 U.S.C. .sctn. 119(e) to U.S. provisional patent application No. 60/393,628, filed on Jul. 3, 2002, entitled "Multi-Slice Network Processor" having inventors Harish R. Devanagondi, Harish P. Belur, Brian A. Petersen, Richard J. Heaton and Majid Torabi, which is hereby incorporated by reference.
This application claims the benefit of priority under 35 U.S.C. .sctn. 119(e) to U.S. provisional patent application No. 60/425,227, filed on Nov. 7, 2002, entitled "Multi-Slice Network Processor" having inventors Harish R. Devanagondi, Harish P. Belur, Brian A. Petersen, Richard J. Heaton and Majid Torabi, which is hereby incorporated by reference.
