Plural scan test paths (401) are provided to reduce power consumed during testing such as combinational logic (101). A state machine (408) operates according to plural shift states (500) to control each scan path in capturing data from response outputs of the combinational logic and then shifting one bit at a time to reduce the capacitive and constant state power consumed by shifting the scan paths.
This application is a divisional of application Ser. No. 10/771,768, filed Feb. 2, 2004, now U.S. Pat. No. 7,155,650, issued Dec. 26, 2006;
Which was a divisional of application Ser. No. 10/336,985, filed Jan. 6, 2003, now U.S. Pat. No. 6,694,467, issued Feb. 17, 2004;
Which was a divisional of application Ser. No. 09/339,734, filed Jun. 24, 1999, now U.S. Pat. No. 6,519,729, issued Feb. 11, 2003;
Which claimed priority from Provisional Application No. 60/090,935, filed Jun. 27, 1998.
