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Top contact alignment in semiconductor devices
 
   
Document Number
US Patent 7494825
Issued Date
February 24, 2009
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Abstract
According to an example embodiment, a semiconductor device includes a lower electrode (316) disposed on an oxide layer (302), an upper electrode (320) disposed on the lower electrode, a dielectric pattern (322) disposed on the oxide layer and surrounding the upper electrode, the upper electrode protruding above an upper surface of the dielectric pattern, and a contact pattern (328) that is contiguous with the upper electrode and the dielectric pattern.
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Number of Claims:
17
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Published
February 24, 2009
Application Number
11/649,094
Filed
January 3, 2007
US Classification
438/3   257/797 257/E23.179 438/692 438/975
Int'l Classification
H01L   21/00   (20060101)   H01L   21/461   (20060101)   H01L   23/544   (20060101)  
Examiner
Assistant Examiner
USPTO Field of Search
438/3   438/673   438/675  
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