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Methods of forming interconnection lines in semiconductor devices
   
Document Number
US Patent 7501340
Issued Date
March 10, 2009
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Abstract
The present disclosure improves characteristics and reliability of a device by preventing seams within a copper layer, wherein seams are created when forming a copper line by a damascene process. Such seams created within a first and a second copper layer are prevented by a process in which the first copper layer and the second copper layer are deposited at constant speeds when the first copper layer is firstly formed only in a via hole by leaving a first copper seed layer only in the via hole, and then the second copper layer is formed in a trench by forming a second copper seed layer in the trench.
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Number of Claims:
20
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Published
March 10, 2009
Application Number
11/317,759
Filed
December 23, 2005
US Classification
438/638   257/E21.579
Int'l Classification
H01L   21/4763   (20060101)  
Examiner
Attorney/Law Firm
Priority Data
Dec 27, 2004 [KR] 10-2004-0113146
USPTO Field of Search
438/675   257/E21.579  
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