A test simulator for simulating a test of a semiconductor device is disclosed, the test simulator including: a test pattern holding unit for holding an existing test pattern to be supplied to the semiconductor device; a device output holding unit for preliminarily holding an output to be obtained from the semiconductor device when the existing test pattern is supplied; a test pattern generating unit for generating a new test pattern to be supplied to the semiconductor device; a test pattern deciding unit for deciding whether the new test pattern is equal to the existing test pattern; and a simulation skipping unit for skipping at least a part of a simulation test by reading an output from the device output holding unit and using the output as an output for the new test pattern without supplying the new test pattern to the semiconductor device when the test patterns are equal to each other.
This is a continuation application of PCT/JP2005/017396 filed on Sep. 21, 2005, which claims priority from a Japanese Patent application No. JP 2004-278582 filed on Sep. 24, 2004, the contents of which are incorporated herein by reference.
