A memory cell device, including a memory material switchable between electrical property states by the application of energy, has bottom and top electrode members and a dielectric material between the two. The bottom and top electrode members have outer, circumferentially-extending surfaces aligned with one another. A memory element, comprising the memory material, at least partially surrounds and electrically contacts the outer surfaces of the top and bottom electrode members to create a memory element transition region at the dielectric material. In some embodiments the top and bottom electrode members and the dielectric element define a stack of material, the stack of material having a length extending in a direction between the top and bottom electrodes and through the dielectric element and a sub lithographically dimensioned width extending perpendicular to the length.
Disclosed herein are new resistive memory devices having one or more buffers layer surrounding a dielectric layer. By inserting one or more buffer layers around the dielectric layer of the device, the resistive ratio of the device is highly enhanced. For example, tests using this unique stack structure have revealed a resistance ratio of approximately 1000.times. over conventional electrode-dielectric-electrode stack structures found in resistive memory devices. This improvement in the resistance ratio of the resistive memory device is believed to be from the improved interface coherence, and thus smoother topography, between the buffer layer(s) and the dielectric layer.
