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Apparatus and method for improving performance of sigma-delta modulators having non-ideal components
   
Document Number
US Patent 7508330
Issued Date
March 24, 2009
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Abstract
In an apparatus and method for improving performance of a third order, double-sampled, sigma-delta modulator (SDM), a first one of three feedback elements included in a feedback loop of the SDM is selected to complete the feedback loop during a first half-cycle of the clock used for the double-sampling. The first one is restricted from being reselected during a subsequent half-cycle of the clock until the first one is reset. A second one of the three feedback elements is selected during a second half-cycle of the clock that is consecutive to the first half-cycle, the second one being different than the first one. A third one of the three feedback elements is selected during a third half-cycle of the clock that is consecutive to the second half-cycle, the third one being different than the second one.
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Number of Claims:
20
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Published
March 24, 2009
Application Number
11/974,142
Filed
October 11, 2007
US Classification
341/143  
Int'l Classification
H03M   3/00   (20060101)  
USPTO Field of Search
341/144   341/155  
Related Patents
7567194 - Delta sigma modulator and delta sigma A/D converter - Owned by Sanyo Electric Co., Ltd. (Moriguchi-shi,JP) Sanyo Semiconductor Co., Ltd. (Ora-gun,JP)

With a delta sigma modulator of this invention, a plurality of clocks required to control a switching circuit can be easily generated and correlation among phases of the plurality of clocks can be automatically maintained while a frequency of the clocks is modified. A ring oscillator is formed of three delay circuits provided with differential amplifiers in the delta sigma modulator. A clock producing circuit produces the plurality of clocks to control the switching circuit by delaying three-phase clocks outputted from the ring oscillator. All the tail currents Ic in the differential amplifiers in the delay circuits in the ring oscillator and the tail currents Ic in the differential amplifiers in the delay circuits in the clock producing circuit are proportional to each other.

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