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Integrated circuit including sub-lithographic structures
 
   
Document Number
US Patent 7514362
Issued Date
April 7, 2009
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Abstract
A method which makes it possible to define in a patterning layer openings having a first dimension that is substantially less than the feature size that can be obtained lithographically includes applying a sacrificial layer made of a material that is different from that of the patterning layer in a predetermined layer thickness on the patterning layer. Afterward, a photoresist layer is applied on the surface of the sacrificial layer, and an opening having a second dimension is defined lithographically in the photoresist layer. Afterward, an etching angle is set in a manner dependent on the layer thickness of the sacrificial layer and also the first and second dimensions, and the sacrificial layer is etched at the etching angle set. Afterward, the patterning layer is etched, the sacrificial layer is removed and a filling material is introduced into the opening produced in the patterning layer.
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Number of Claims:
11
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Owner
Published
April 7, 2009
Application Number
11/258,367
Filed
October 26, 2005
US Classification
438/672   438/640 438/675
Int'l Classification
H01L   21/44   (20060101)  
Attorney/Law Firm
Priority Data
Oct 29, 2004 [DE] 10 2004 052 611
USPTO Field of Search
438/629   438/637   438/638   438/640   438/668   438/672   438/673   438/675  
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