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Semiconductor device and manufacturing method thereof
   
Document Number
US Patent 7514792
Issued Date
April 7, 2009
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Abstract
After an interlayer insulation film (1) and a CMP stopper film are formed, wiring trenches are formed. Next, after a barrier metal film (4) and a Cu film (5) are buried in the wiring trenches, the Cu film (5) and the barrier metal film (4) are planarized by CMP or the like until the CMP stopper film is exposed, whereby lower wirings (17) are formed. Next, the CMP stopper film is removed by dry etching, so that surfaces of the lower wirings (17) relatively protrude from their surrounding area. Subsequently, an etching stopper film (6) is formed on the entire surface. Thereafter, via plugs (18) are formed, and upper wirings (19) are further formed in the same manner as the lower wirings (17).
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Number of Claims:
5
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Owner
Fujitsu Limited (Kawasaki,JP)
Published
April 7, 2009
Application Number
11/393,655
Filed
March 31, 2006
US Classification
257/758   257/774 257/E23.145
Int'l Classification
H01L   23/48   (20060101)   H01L   23/52   (20060101)  
Examiner
Parent Case
This application is a continuation of international PCT/JP2003/12671, filed on Oct. 2, 2003.
USPTO Field of Search
257/758   257/774   257/E23.145  
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