Power conservation via DRAM access reduction is provided by a buffer/mini-cache selectively operable in a normal mode and a buffer mode. In the buffer mode, entered when CPUs begin operating in low-power states, non-cacheable accesses (such as generated by a DMA device) matching specified physical address ranges are processed by the buffer/mini-cache, instead of by a memory controller and DRAM. The buffer/mini-cache processing includes allocating lines when references miss, and returning cached data from the buffer/mini-cache when references hit. Lines are replaced in the buffer/mini-cache according to one of a plurality of replacement policies, including ceasing replacement when there are no available free lines. In the normal mode, entered when CPUs begin operating in high-power states, the buffer/mini-cache operates akin to a conventional cache and non-cacheable accesses are not processed therein. In one usage scenario, data retained in the buffer/mini-cache is graphics refresh data maintained in a compressed format.
CROSS REFERENCE TO RELATED APPLICATIONS
Priority benefit claims for this application are made in the accompanying Application Data Sheet (if any). To the extent permitted by the type of the instant application, this application incorporates by reference for all purposes the following applications, which are all owned by the owner of the instant application: U.S. Provisional Application Ser. No. 60/736,632 filed Nov. 14, 2005, by Laurent R. Moll, et al., and entitled POWER CONSERVATION VIA DRAM ACCESS REDUCTION; U.S. Provisional Application Ser. No. 60/736,736 filed Nov. 15, 2005, by Laurent R. Moll, et al., and entitled A SMALL AND POWER-EFFICIENT CACHE THAT CAN PROVIDE DATA FOR BACKGROUND DMA DEVICES WHILE THE PROCESSOR IS IN A LOW-POWER STATE; and U.S. Provisional Application Ser. No. 60/761,220 filed Jan. 23, 2006, by Laurent R. Moll, et al., and entitled POWER CONSERVATION VIA DRAM ACCESS REDUCTION.
