A carrier for use in a chip-scale package includes a semiconductor substrate with a plurality of apertures formed therethrough. The apertures of the carrier are aligned with bond pads of a semiconductor device. Conductive material is introduced into each of the apertures of the carrier to form vias therein that establish electrical communication between the bond pads of the semiconductor device and conductive traces that extend to the vias or contacts or conductive structures that are subsequently formed directly over the vias or at opposite ends of the conductive traces. Such chip-scale packages may be formed on a wafer-scale, in which case individual chip-scale packages are singulated from one another at some point during or following the packaging process.
CROSS-REFERENCE TO RELATED APPLICATION
This application is a divisional of application Ser. No. 09/652,495, filed Aug. 31, 2000, now U.S. Pat. No. 7,271,491, issued Sep. 18, 2007.
