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Document Number
US Patent 7518900
Issued Date
April 14, 2009
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Abstract
A memory capable of reducing the memory cell size is provided. This memory includes a plurality of memory cells including diodes, a plurality of bit lines and a first conductive type first impurity region arranged to intersect with the bit lines for functioning as first electrodes of the diodes included in the memory cells and a word line. The first impurity region is divided every bit line group formed by a prescribed number of bit lines along a direction intersecting with the extensional direction of the first impurity region.
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Number of Claims:
17
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Published
April 14, 2009
Application Number
11/489,535
Filed
July 20, 2006
US Classification
365/103   365/105 365/115 365/185.13 365/243
Int'l Classification
G11C   17/00   (20060101)  
Examiner
Attorney/Law Firm
Priority Data
Jul 22, 2005 [JP] 2005-213225
USPTO Field of Search
365/103   365/105   365/115   365/243   365/185.15   365/185.13  
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