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IO self test method and apparatus for memory
   
Document Number
US Patent 7519891
Issued Date
April 14, 2009
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Inventors
Zimmerman; David J. (El Dorado Hills, CA)
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Abstract
A memory includes a data generator to generate a data pattern, a transmitter in communication with the data generator, the transmitter to transmit the data pattern as a test data pattern, receiver to receive the test data pattern from the transmitter, and a comparator coupled with the receiver, the comparator to compare the data pattern with the test data pattern from the receiver and to verify proper operation of a memory channel. A method includes providing a seed value to a transmit and a receive pattern generator in a memory, generating data at the transmit pattern generator from the seed value and transmitting the data from the memory, looping the data to a receiver on the memory, using the seed value to generate data with the receive pattern generator, and comparing the data from the receive pattern generator and the transmit pattern generator to determine if any errors occurred.
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Number of Claims:
6
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Owner
Intel Corporation (Santa Clara, CA)
Published
April 14, 2009
Application Number
11/238,897
Filed
September 28, 2005
US Classification
714/738  
Int'l Classification
G01R   31/28   (20060101)  
Attorney/Law Firm
USPTO Field of Search
714/738  
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