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Biasing current to speed up current mirror settling time
   
Document Number
US Patent 7522002
Issued Date
April 21, 2009
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Abstract
A current mirror circuit includes a first current-mirror transistor coupled to a second current-mirror transistor. A load is coupled to the second current-mirror transistor. A first current source is coupled to the first current-mirror transistor to cause a bias current to flow through the first current-mirror transistor and a second current source is coupled to the second current-mirror transistor and in parallel with the load to shunt the bias current away from the load.
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Number of Claims:
23
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Owner
Atmel Corporation (San Jose, CA)
Published
April 21, 2009
Application Number
11/619,729
Filed
January 4, 2007
US Classification
330/288  
Int'l Classification
H03F   3/04   (20060101)  
Examiner
USPTO Field of Search
330/288   323/315   323/316   327/538   327/543  
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