A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106,and controller 110 remain the same as in the known art. The changes between the known art Scan-BIST architecture and the low power Scan-BIST architecture involve modification of the known scan path into scan path 502, to insert scan paths A 506, B 508 and C 510, and the insertion of an adaptor circuit 504 in the control path 114 between controller 110 and scan path 502.
This application is a divisional of application Ser. No. 10/886,206, filed Jul. 6, 2004, now U.S. Pat. No. 7,051,257, issued May 23, 2006; Which was a divisional of application Ser. No. 09/803,608, filed Mar. 9, 2001, now U.S. Pat. No. 6,763,488, issued Jul. 13, 2004;
Which claimed priority from Provisional Application 60/188,109, filed Mar. 9, 2000.
The disclosure relates to and incorporates by reference U.S. Pat. No. 6,519,729, issued Feb. 11, 2003, and U.S. Pat. No. 6,769,080, issued Jul. 27, 2004.
