or
Bookmark and Share
Integrated circuit arrangement and method
   
Document Number
US Patent 7529999
Issued Date
May 5, 2009
Link
Inventors
Map
Abstract
An integrated circuit arrangement including at least one circuit part which is designed to run through a functional self test and to output test results of the functional self test, and a testing unit, which is coupled to an input and an output and which is coupled to the at least one circuit part via testing lines. The testing unit is designed to start the functional self test when a starting signal for the functional self test is applied to the input, to evaluate test results that are present to determine whether they have a predefined relationship with predefined values, and to output data indicating the test result at the output. The testing unit is also designed to start the functional self test by internal circuit means and to evaluate the test results present.
Tags:
Description:
Amusing 0%
Clever 0%
Complex 0%
Efficient 0%
Historic 0%
Important 0%
Innovative 0%
Interesting 0%
Practical 0%
Simple 0%
Number of Claims:
21
Comments:
no comments yet
Published
May 5, 2009
Application Number
11/530,262
Filed
September 8, 2006
US Classification
714/734  
Int'l Classification
G01R   31/28   (20060101)  
Attorney/Law Firm
Priority Data
Sep 08, 2005 [DE] 10 2005 042 790
USPTO Field of Search
714/733   714/734  
Related Patents
Claims
Description
About| FAQs| Terms & Disclaimer| Link to Us| Contact Us