When a signal output by a solid-state image sensing device is clamped to a predetermined reference potential, a high voltage generated in a transfer suspension period after the clamping as generally supplied to an A/D converter is generated. A sample/hold output Va is clamped to a clamp level Vref over a period of time between a halfway point of time of a signal of a picture element preceding ahead by one line and the end of an inhibit period of transfer clocks of a signal output by an empty transmission unit via a first clamp pulse and a sample/hold output for the second picture element, or a subsequent one of an ORB unit is clamped to the clamp level via a second clamp pulse to prevent a signal output from exceeding a reference voltage from being supplied to an A/D converter at a later stage.
RELATED APPLICATION
This application is a continuation application of application Ser. No. 10/247,557, filed on Sep. 20, 2002, now U.S. Pat. 7,071,977 which is a divisional application of application Ser. No. 08/676,731, filed on Jul. 8, 1996, now U.S. Pat. No. 6,480,228, the entire contents of which are being incorporated herein by reference.
